The present invention relates to a CMOS integrated circuit (hereinafter referred to as a “CMOS IC”). Specifically, the invention relates to a CMOS IC that protects devices in an integrated circuit from a surge of voltage caused by static electricity and such applied to a power supply line.
When a surge of voltage caused by static electricity and such is applied to a power supply (VCC) line, the surge voltage exceeds the breakdown voltage of the device, which constitutes a CMOS IC, e.g. a series regulator circuit manufactured by the CMOS process, and sometimes breaks down the device.
FIG. 2 is a circuit diagram showing a configuration of a conventional CMOS IC. In detail, a conventional CMOS integrated circuit (hereinafter referred to as “CMOS IC”) 400 shown in FIG. 2 constitutes a series regulator circuit manufactured by the CMOS process. The conventional CMOS IC 400 feeds an output current to a load 418 via a P-channel double-diffused metal-oxide-semiconductor transistor Qo (410) for feeding an output (hereinafter referred to as “outputting PDMOS transistor Qo (410)”). The CMOS IC 400 is provided with a control system that controls output voltage (VREG) 4 at a certain value, even when a variation is caused in a power supply (VCC) 1 or the load 418.
The control system detects an output voltage (VREG) 4 applied to the load 418 as a divided voltage from a connection point 421 of a voltage divider circuit including dividing resistors R1 (419) and R2 (420) via node 417. The control system feeds the divided voltage detected to the gate of P-channel MOSFET (hereinafter referred to as “PMOSFET”) 513 that constitutes a differential amplifying pair of differential input stage 510 in operational amplifier section 500. Reference voltage (VREF) 2 is fed to the gate of another PMOSFET 512 that constitutes the differential amplifying pair. Reference voltage (VREF) 2 and the divided voltage detected are compared with each other. When reference voltage (VREF) 2 is higher than the divided voltage, the control system increases the output current from outputting PDMOS transistor Qo (410) to raise output voltage (VREG) 4. When the divided voltage is higher than reference voltage (VREF) 2, the control system decreases the output current from outputting PDMOS transistor Qo (410) to lower output voltage (VREG) 4. The Patent Document 1 describes in detail a series regulator circuit including the control system as described above.
The differential input stage 510 in the operational amplifier section 500 is connected to the line of power supply (VCC) 1. The Differential input stage 510 includes constant current supply 511 that makes a constant current flow to the sources of PMOSFET's 512 and 513, a differential amplifying pair including PMOSFET's 512 and 513, and a current mirror circuit including two N-channel MOSFET's (hereinafter referred to as “NMOSFET's”) 516 and 517 that make an equal current flow to PMOSFET's 512 and 513.
The operational amplifier section 500 includes an output stage 520 including resistor Rg (521) and NMOSFET Qn (524). The operational amplifier section 500 also includes a feedback circuit including feedback capacitor Cfb (532) for phase compensation and feedback resistor Rfb (531) for phase compensation, both connected between differential input stage 510 and output stage 520.
The connection point 514 of the drain of PMOSFET 513 working for the output port of the differential input stage 510 and the drain of NMOSFET 517 is connected via feedback capacitor Cfb (532) for phase compensation and feedback resistor Rfb (531) for phase compensation to the drain of NMOSFET Qn (524). The connection point 514 of the drain of PMOSFET 513 and the drain of NMOSFET 517 is connected via a gate terminal node Vgp (522) to the gate of the outputting PDMOS transistor Qo (410). The connection point 515 of the drain of PMOSFET 513 working for the output port of differential input stage 510 and the drain of NMOSFET 517 is connected to the gate of NMOSFET Qn (524). The drain of NMOSFET Qn (524) is connected to the line of power supply (VCC) 1 via resistor Rg (521) and to the gate of outputting PDMOS transistor Qo (410) via gate terminal node Vgp (522). Zener diode 422 is disposed for protecting the gate of outputting PDMOS transistor Qo (410) from a high voltage.
In order to protect devices in the integrated circuit from a surge caused by static electricity and such applied to the power supply line, conventional CMOS IC 400 shown in FIG. 2 operates in the following manner, namely, outputting PDMOS transistor Qo (410) and NMOSFET Qn (524) that controls the output from outputting PDMOS transistor Qo (410) conduct the surge applied to the line of power supply (VCC) 1 through themselves to prevent the devices constituting the integrated circuit from being be broken down.
Now the protection operation described above will be investigated below. When a surge caused by static electricity and such is applied to the line of power supply (VCC) 1, the voltage on the line of power supply (VCC) 1 rises rapidly (a surge voltage is caused). In this case, conventional CMOS IC 400 shown in FIG. 2 discharges the surge superposed on the line of power supply (VCC) 1 through the mechanism described below.
First, the surge voltage is applied directly to the source of outputting PDMOS transistor Qo (410), forming the source potential of outputting PDMOS transistor Qo (410). In addition to this, the divided voltage obtained by dividing the surge voltage with capacitance Cgs (404) between the gate and source of outputting PDMOS transistor Qo (410), capacitance Cgd (402) between the gate and drain of outputting PDMOS transistor Qo (410) and capacitance Cg (406) is applied to the gate of outputting PDMOS transistor Qo (410), forming the gate potential of outputting PDMOS transistor Qo (410). As a result, outputting PDMOS transistor Qo (410) is brought into the ON-state thereof. In other words, the source potential of outputting PDMOS transistor Qo (410) rises rapidly as soon as the voltage on the line of (VCC) 1 rises rapidly. As described above, the division of the surge voltage with capacitors Cgs (404), Cgd (402) and Cg (406) forms the gate potential of outputting PDMOS transistor Qo (410). Although the gate potential of outputting PDMOS transistor Qo (410) changes corresponding to the voltage change on the line of (VCC) 1, the gate potential of outputting PDMOS transistor Qo (410) does not rise so high as the source potential thereof. Due to the potential scheme described above, the voltage between the source and gate of outputting PDMOS transistor Qo (410) rises, bringing outputting PDMOS transistor Qo (410) into the ON-state thereof. Outputting PDMOS transistor Qo (410) in the ON-state thereof makes a current flow to load 418. Here, it is assumed that capacitance Cgs (404) includes the gate capacitance of outputting PDMOS transistor Qo (410). Capacitance Cg (406) represents the floating capacitance around NMOSFET Qn (524).
Second, the gate voltage of NMOSFET Qn (524) is raised by the voltage rising rapidly on the line of power supply (VCC) 1 via resistor Rg (521), feedback resistor Rfb (531) for phase compensation and feedback capacitor Cfb (532) for phase compensation, bringing NMOSFET Qn (524) into the ON-state thereof. NMOSFET Qn (524) in the ON-state thereof makes a current flow from the line of power supply (VCC) 1 to ground (GND) 3 and lowers the voltage of gate terminal node Vgp (522). As the voltage of gate terminal node Vgp (522) is lowered, outputting PDMOS transistor Qo (410) is brought further deep into the ON-state thereof. [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2006-318204
The conventional CMOS IC 400 increases the output current therefrom to prevent the circuit devices from being broken down by the surge superposed on the power supply line. However, for increasing the output current, it is necessary to enlarge the size of outputting PDMOS transistor Qo (410). As the size of outputting PDMOS transistor Qo (410) is enlarged, capacitance Cgs (404) between the gate and drain of outputting PDMOS transistor Qo (410) becomes higher. For stabilizing the feedback system, it is necessary to enlarge feedback resistor Rfb (531) and feedback capacitor Cfb (532). As capacitance Cgs (404) between the gate and drain of outputting PDMOS transistor Qo (410) becomes higher, it is easier for the potential at the gate terminal node Vgp (522) to follow the voltage on the line of power supply (VCC) 1 and it is harder for outputting PDMOS transistor Qo (410) to be ON.
For stabilizing the feedback system, the product of feedback resistance Rfb (531) and feedback capacitance Cfb (532) is increased generally. Since the rise of the capacitor capacitance in an integrated circuit adversely affects the area of the integrated circuit greatly, it is practical to enlarge feedback resistor Rfb (531). However, as the feedback resistor Rfb (531) becomes larger, the impedance to the gate terminal of NMOSFET Qn (524) becomes higher, making it hard to transmit the variations caused in the power supply (VCC) 1 and at gate terminal node Vgp (522) to the gate of NMOSFET Qn (524). As a result, it is hard for NMOSFET Qn (524) to be ON. Therefore, a too-high surge voltage is applied to NMOSFET Qn (524), breaking down NMOSFET Qn (524) sometimes.
In view of the foregoing, it would be desirable to provide a CMOS integrated circuit (CMOS IC) that makes a switch to be triggered to operate, when a surge caused by static electricity and such is applied to a power supply line, by the potential change at a node corresponding to the potential change of the power supply line for preventing the circuit device in the IC from being broken down.